The present invention relates to fin field-effect transistor (FinFET) devices, and more specifically, to fully confined epitaxial growth for continued pitch scaling in FinFET devices.
Epitaxy is often used to merge individual fins that belong to a single transistor in order to provide enough material in the source drain for silicidation as well as to relax the requirements on a contact. Conventional epitaxy processes are not self-limited. This means that there is a variation in epitaxy thickness based on the fin-to-fin spacing to ensure that all fins that need to be merged are merged.
However, there is a need to avoid unwanted shorts between neighboring transistors, such as neighboring n-type field effect (nFET) transistors and p-type field effect (pFET) transistors, as well as a source to drain shorts caused by the merging of fins of different transistors. The variation in the epitaxy thickness makes it difficult to design growth rates to avoid the unwanted shorts. Known methods have employed extra spacing between neighboring transistors or have employed fin height scaling. However, extra spacing, for example, is not compatible with area and performance scaling.
There is a need for an improved method for finFET manufacture that prevents the unwanted shorts between n-FET and p-FET transistor regions.